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RTL Compiler: Manually Add Logic Gates

moogyd

Hi,

I am trying to update some old (bgx_shell) scripts to RTL compiler (10). 

This script basically performs some very basic logic isolation, but including AND gates.

e.g. Within i_subdes1 there is a net RC_TESTPORT

i_subdes1/RC_TESTPORT to connected to

- i_subdes1/i_subdes2/RC_TESTPORT

- i_subdes1/i_subdes3/RC_TESTPORT

I want to add an AND gate such that

i_subdes1/RC_TESTPORT connected to i_subdes/i_newgate/A1

i_subdes1/ISOLATE connected to i_subdes/i_newgate/A2

i_subdes1/i_newgate/X connected to  i_subdes1/i_subdes2/RC_TESTPORT

i_subdes1/i_newgate/X connected to  i_subdes1/i_subdes3/RC_TESTPORT

With bgx_shell, I used create_instance, delete_netconn, add_netconn and create_net. There are obvious alternatives for the first 3, but I am not sure about create_net. 

I tried a simple experiment, and it connected RC_TESTPORT to i_newgate/A1 OK, but didn't manage to connect the AND gate output - it seemed to try and connect RC_TESTPORT to both the input and output of the AND gate. 

I am not sure I understand where to use NETs and PORTs.

Does anyone have a script (or link) to a script that does something similar?

Thanks,

Steven

 

 

Parents

  • Hi,

    Just an update.

    I now have a solution - my previous problem was that I was confustion re pins/ports, and also not correctly making changes at the correct level of hierachy.

    I would still be interested in comparing my solution with other scripts that may be available.

     Thanks,

    Steven

Reply

  • Hi,

    Just an update.

    I now have a solution - my previous problem was that I was confustion re pins/ports, and also not correctly making changes at the correct level of hierachy.

    I would still be interested in comparing my solution with other scripts that may be available.

     Thanks,

    Steven

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