Hi developers! :)
I've faced with problem with defining of timing constraint in RTL Compiler. In my design inner clock is generated based on signals from two input pins (xor on two signals actually). How can i tell to RTL Compiler, that this inner signal is a clock? I tried create_generated_clock, but it allows to define generated clock only based on some input pin. This is unacceptable for my design. It also seems to me, that create_generated_clock can be used only for creating clock on outputs of deviders or pll.
Thanks in advance, Evgeniy
I would try creating a module whose output is the needed clock. From there on, it would be a input pin for rest of the design.You can also possibly create constraint as it is an output for the module. This change would fit the RTL compiler requirements.
Thank you very much for the answer. For me it's very important to learn how to define clocks on design inner signals. It was the requirement for my project. So i did this in the following manner:
set C_D [define_clock -name CLOCK_D -domain d_5 -period 10000 [find /designs/upper_prj/inner_comp -pin q]]
RTL compiler did not tell me anything bad about this construction. Is it ok, how do you think?
I'll try, thank you =)