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RTL compiler inner clock definition

EvgeniySUAI

 Hi developers! :)

I've faced with problem with defining of timing constraint in RTL Compiler. In my design inner clock is generated based on signals from two input pins (xor on two signals actually).  How can i tell to RTL Compiler, that this inner signal is a clock? I tried create_generated_clock, but it allows to define generated clock only based on some input pin. This is unacceptable for my design. It also seems to me, that create_generated_clock can be used only for creating clock on outputs of deviders or pll.

Thanks in advance, Evgeniy

 

 

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