Long Run Times

 Hi Suresh,

I am on the third time replying to this message due to my fabulous browser, NOT :(

Anyhow, 365K flops is certainly doable for RC. In fact, I am currently working on a design of 1.3M flops and 9M instances so not a problem. That being said, there are other reason why you MAY want to split it. This will improve your turnaround time at the possible expense of QoR as well as the need for add'l scripts.

As per you debug questions, it would be helpful if you can provide more detail as follows

(1) Are you using N2N or your own scripts ?

(2) Starting from netlist or HDL ?

(3) if netlist, were you meeting timing ?

(4) What is your information_level set to ?

(5) You say hung but what does that exactly mean ? 1 hour ? 10 hours ? 10 days ?

(6) what runtime did you expect ? Memory ?

(7) what version of RC are you using (found at top of log) ?

(8) what effort level are you running for syn -to_gen ? syn -to_map ? syn -to_placed ?

(9) what are your runtime for some of the stages that complete ?

 Not trying to flood you with questions but there is not much that we can do to help without answers to some of those questions

regards,

gh-

Hi gh, 

please find my answers below 

(1) Are you using N2N or your own scripts ?

(2) Starting from netlist or HDL ?

    >>  I started synthesizing HDL not the netlist. 

(3) if netlist, were you meeting timing ?

(4) What is your information_level set to ?

    >> information_level is set to 7 

(5) You say hung but what does that exactly mean ? 1 hour ? 10 hours ? 10 days ?

     >> It is been like this from 1st Feb  21:30 ( IST) 

(6) what runtime did you expect ? Memory ?

    >> this is the first time i am running this RTL and hence i have no good idea on how much  time the Design will run for..

   >> MEM: 5338 Mbytes;  SWAP: 12904 Mbytes;  NTHREAD: 4

(7) what version of RC are you using (found at top of log) ?

     EDI/09.12.00 

(8) what effort level are you running for syn -to_gen ? syn -to_map ? syn -to_placed ?

    syn -to_gen  -->  medium effort 

   syn -to_map  -no_incr --> high effor 

   syn -to_map  -incr  --> high effort 

(9) what are your runtime for some of the stages that complete ?

      syn -to_gen  took 1r 30min 25 sec

 Hope the above information would help you to make some suggestion...!!! 

In one of the designs, there are around 300 levels in the design and i would like to analyze these kind of issues, @ elaboration phase.. not that i would run for 10 hrs and find such issues.. any ideas on this would be really helpful .. 

Thanks

suresh 

Hi gh, 

the RC version is  v09.10-p104_1.

thanks

suresh 

 Hi Suresh,

thanks for your reply. 9.1-p004 is early 2009 so, as a first step, I would move to a newer release since your run, while it may complete, seems has definitely hit a bug. I am currently using RC10.10.200, Version: RC10.1-s202 and had good luck with it. Bear in mind your runtime will still be long (at least I would expect) but certainly complete. Also, what tool generated your starting netlist ?

As per reviewing some of the upfront metrics, since you are starting from netlist, you can just stop after applying the constraints and perform the analysis. I certainly do not know much about your design but 300 levels of logic certainly seems like a recepie for trouble

Last but not least, I am assuming you cannot post much more detail on the forum so you may want to contact your local AE who will be able to look at the design with you and give you more guidance. 

gh-

Hey gh,

Thanks for your suggestion..

Do you want me to check anythign from the log file, or any tricky commands to enable the state of processing ????

 Regarding the 300+ logic levels,  we fixed it .. it was a bad usage of datapath compnonents.. however, i wish i would catch these issues before synthesizing ..not after completion of synthesis and fix thm back ..this costed me almost a day .. 10hr runtime !!

 Any tricks in analysizing or guessing  such issues will be a help....

thanks

suresh 

 Hi Suresh,

glad to hear you were able to address the issue. In your case, since the input is netlist, there are all sort of metrics that you can take a look before synthesizing. I would start with report qor and report timing for each cost group but you can also look at many other metrics beyond this reports such as area report, logic level depth, etc.

 If you were starting from HDL, it is a little more challenging since there is some level of chicken and egg. In other words some problems cannot be identified until you have initial gates. That being said, RC provide lots of information such as the global_map target and globa_incr target paths in the logs where a 300 deep path would have been fairly evident. You would have still incurred some of the runtime but only about 30%.

good luck,

gh-