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Long Run Times

sureshm

 Hi

   I am using EDI-09.12.00 version for my synthesis. 

I am not aware of the total design size, but the total number of the flops in the design are around 365k. 

I am wondering if the tool has the capability of handling such high instance count.

I am seeing a lot of run times being there.. it stops after 

Synthesizing to gates
Tue Feb 01 21:33:19 IST 2011
Mapping mydesign to gates.
      Mapping 'mydesign'...
        Preparing the circuit
          Pruning unused logic
 

 I am not sure whether

1) The tool is proecssing any data internally 

2) or the tool got hung there.. 

 

how do i debug the reason for the long run times. 

Thanks

suresh 

 

Parents

  • Hi gh, 

    please find my answers below 

    (1) Are you using N2N or your own scripts ?

    (2) Starting from netlist or HDL ?

        >>  I started synthesizing HDL not the netlist. 

    (3) if netlist, were you meeting timing ?

    (4) What is your information_level set to ?

        >> information_level is set to 7 

    (5) You say hung but what does that exactly mean ? 1 hour ? 10 hours ? 10 days ?

         >> It is been like this from 1st Feb  21:30 ( IST) 

    (6) what runtime did you expect ? Memory ?

        >> this is the first time i am running this RTL and hence i have no good idea on how much  time the Design will run for..

       >> MEM: 5338 Mbytes;  SWAP: 12904 Mbytes;  NTHREAD: 4

    (7) what version of RC are you using (found at top of log) ?

         EDI/09.12.00 

    (8) what effort level are you running for syn -to_gen ? syn -to_map ? syn -to_placed ?

        syn -to_gen  -->  medium effort 

       syn -to_map  -no_incr --> high effor 

       syn -to_map  -incr  --> high effort 

    (9) what are your runtime for some of the stages that complete ?

          syn -to_gen  took 1r 30min 25 sec

     Hope the above information would help you to make some suggestion...!!! 

    In one of the designs, there are around 300 levels in the design and i would like to analyze these kind of issues, @ elaboration phase.. not that i would run for 10 hrs and find such issues.. any ideas on this would be really helpful .. 

     

    Thanks

    suresh 

Reply

  • Hi gh, 

    please find my answers below 

    (1) Are you using N2N or your own scripts ?

    (2) Starting from netlist or HDL ?

        >>  I started synthesizing HDL not the netlist. 

    (3) if netlist, were you meeting timing ?

    (4) What is your information_level set to ?

        >> information_level is set to 7 

    (5) You say hung but what does that exactly mean ? 1 hour ? 10 hours ? 10 days ?

         >> It is been like this from 1st Feb  21:30 ( IST) 

    (6) what runtime did you expect ? Memory ?

        >> this is the first time i am running this RTL and hence i have no good idea on how much  time the Design will run for..

       >> MEM: 5338 Mbytes;  SWAP: 12904 Mbytes;  NTHREAD: 4

    (7) what version of RC are you using (found at top of log) ?

         EDI/09.12.00 

    (8) what effort level are you running for syn -to_gen ? syn -to_map ? syn -to_placed ?

        syn -to_gen  -->  medium effort 

       syn -to_map  -no_incr --> high effor 

       syn -to_map  -incr  --> high effort 

    (9) what are your runtime for some of the stages that complete ?

          syn -to_gen  took 1r 30min 25 sec

     Hope the above information would help you to make some suggestion...!!! 

    In one of the designs, there are around 300 levels in the design and i would like to analyze these kind of issues, @ elaboration phase.. not that i would run for 10 hrs and find such issues.. any ideas on this would be really helpful .. 

     

    Thanks

    suresh 

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