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cadence RTL compiler...WNS (Worse Negative slack)

ChInNi miSSing
Respected all,
Am synthesizing my HDL code using cadence RTL compiler. Am getting a slack of -14586 ps my clock was 10 ns.
i need to optimize my slack to a small positive value, and my critical path is between a reg to reg (C2C). 
for doing this i need to apply some constraints na, i have applied output delay, input_delay constraints, but in order to apply these constraints the critical path should be between input and output pins, so no changes have done to the slack and critical path.

please guide me something to overcome this negative slack...

Next, Is it possible to increase the size of a particular gate  to reduce the delay of that particular cell in the design during synthesis using some commands or anything ???
If, so please guide me....
waiting for u r reply
thanking you all..
Parents
  •  As per guide, I would think the documentation and the write_template command are the best places to start

    Without a timing report of the path in question, it is pretty hard if not impossible to tell what the problem is.

    10ns cycle time is ample cycle time in most modern libraries so it sounds like you are failing to synthesize or have

    Not constrained the design properly. RC will always optimize to meet timing given your constraints.

    At a minimum you should make sure you provide the following constraints:

    + clock

    + input delays

    + output delays

    Note that even a design without flops would most likely have clocks since input and output would have a clock reference

    As per resizing cells, that can certainly be done manually but should happen automatically if properly constrained

    Gh-

     
Reply
  •  As per guide, I would think the documentation and the write_template command are the best places to start

    Without a timing report of the path in question, it is pretty hard if not impossible to tell what the problem is.

    10ns cycle time is ample cycle time in most modern libraries so it sounds like you are failing to synthesize or have

    Not constrained the design properly. RC will always optimize to meet timing given your constraints.

    At a minimum you should make sure you provide the following constraints:

    + clock

    + input delays

    + output delays

    Note that even a design without flops would most likely have clocks since input and output would have a clock reference

    As per resizing cells, that can certainly be done manually but should happen automatically if properly constrained

    Gh-

     
Children
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