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cadence RTL compiler...WNS (Worse Negative slack)

ChInNi miSSing
Respected all,
Am synthesizing my HDL code using cadence RTL compiler. Am getting a slack of -14586 ps my clock was 10 ns.
i need to optimize my slack to a small positive value, and my critical path is between a reg to reg (C2C). 
for doing this i need to apply some constraints na, i have applied output delay, input_delay constraints, but in order to apply these constraints the critical path should be between input and output pins, so no changes have done to the slack and critical path.

please guide me something to overcome this negative slack...

Next, Is it possible to increase the size of a particular gate  to reduce the delay of that particular cell in the design during synthesis using some commands or anything ???
If, so please guide me....
waiting for u r reply
thanking you all..
Parents

  • Respected  Gh,

    thank you so much for u r reply

    i have defined my clock like this with a 10 ns time period

    define_clock -name clk -period 10000 [find / -port clk]

    and i am giving input and output delay of 1.5 ns to all inputs and outputs.

    then also am getting negative slack. then how to reduce the delay using RTL compiler commands 

Reply

  • Respected  Gh,

    thank you so much for u r reply

    i have defined my clock like this with a 10 ns time period

    define_clock -name clk -period 10000 [find / -port clk]

    and i am giving input and output delay of 1.5 ns to all inputs and outputs.

    then also am getting negative slack. then how to reduce the delay using RTL compiler commands 

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