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RTL Compiler: write_sdf and clocks

moogyd

Hi,

I am trying to run some pre-layout gate level simulations for a design. The design contains clock gating, and no clock trees.

I would like to assume an ideal clock tree, and would be happy to exclude all timing associated with the clock paths (i.e. set to 0).

Is there any way of acheiving this with the write_sdf command. i.e. Set all delays associated with clocks (or ideal_nets) to be 0?

Thanks,

Steven

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  •  Hi Steven,

     

      In RTLCompiler th clock path are by default ideal. So unless you have added a set_clock_latency on your clock rc will assume 0. In the sdf file using 'write_sdf -interconn interconnect' will crt the net values where you can see the clock wire delay is forward annotated to the arrival pin as 0.0.

     

    Cheers,

      Mike

Reply

  •  Hi Steven,

     

      In RTLCompiler th clock path are by default ideal. So unless you have added a set_clock_latency on your clock rc will assume 0. In the sdf file using 'write_sdf -interconn interconnect' will crt the net values where you can see the clock wire delay is forward annotated to the arrival pin as 0.0.

     

    Cheers,

      Mike

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