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RTL Compiler: write_sdf and clocks

moogyd

Hi,

I am trying to run some pre-layout gate level simulations for a design. The design contains clock gating, and no clock trees.

I would like to assume an ideal clock tree, and would be happy to exclude all timing associated with the clock paths (i.e. set to 0).

Is there any way of acheiving this with the write_sdf command. i.e. Set all delays associated with clocks (or ideal_nets) to be 0?

Thanks,

Steven

Parents

  • Hi Mike,

    The actual delays I was concerned about are the path delays through the integrated clock gate cells. I was hoping that these would be set to 0, but the are  not.

     Any other suggestions (other than editing the SDF file ;-) )

    Thanks,

    Steven 

Reply

  • Hi Mike,

    The actual delays I was concerned about are the path delays through the integrated clock gate cells. I was hoping that these would be set to 0, but the are  not.

     Any other suggestions (other than editing the SDF file ;-) )

    Thanks,

    Steven 

Children
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