RTL Compiler : Giving 1'b0 in synthesized netlist

Hi all,

 I have application  where I have to use a set-reset D flip flop and I need to connect the D input to set port of the flop. 

I have written the RTL code for the same as a single bit flop and instatiated the flop as a 256 bit wide register as shown below

====================================

set_reset_dff  u_shell_output_cap_dff[255:0]
(
  .d          (q_int[255:0]),
  .set        (q_int[255:0]),
  .reset      (RST),
  .clk        (clk),
  .q          (Q[255:0])
);

====================================

However after  synthesis in the netlist I see following code with 1'b0 on the D input and where ever the flop is instantiated there also I see 1'b0 on D input. Basically RTL compiler is not connecting the set and D input of the flop. Any ideas what could be the reason? Is there a way to force it to short set and D input. I have also used "generate" to instatiate flop iso the code snippet above but see same result...

=============================================

module set_reset_dff(d, set, reset, clk, q);
  input d, set, reset, clk;
  output q;
  wire d, set, reset, clk;
  wire q;
  wire n_0, n_1;
  df3qx2pdv q_reg(.CD (n_1), .SD (n_0), .CP (clk), .D (1'b0), .Q (q));
  ivpdv g19(.A (reset), .Z (n_1));
  ivpdv g20(.A (set), .Z (n_0));
endmodule
 ==================================================

 Thanks,

-DN