RTL compiler: how to do bottom-up synthesis

Hi

Do you have to stick to bottom-up? From what I understand DC users do bottom-up because of capacity limitations. You should find the capacity to be higher in RC, probably allowing you to switch to top-down.

Chrystian

I want to how to do bottom-up synthesis using RC.

Could you please give some suggestions?

Thanks very much!

Hi airland,

not sure what you are after. Synthesis tools do not know what you are gonig to do with the netlist so you can always use a synthesized netlist at the next level up. What are the specific of your bottom-up question ? For fast designs I would argue that Top-down traditionally yields better results. The benefits of top-down are various:

- single scripts environment to maintain

- no need to budget/guesstimate I/O delays

- better optimization of constant driven paths

This is not to say there are no benefits to running bottom up but the motivation you mention is better suited for top-down than bottom-up IMHO. In anycase, as per your original question, please clarify what aspects you are looking for and we can try to better help you

 regards,

gh-

Thanks for your kindly reply. I know top-down is better. I just want to know how to do bottom-up synthesis.

My question is as following:

read the whole design for one time and then use like DC's set current_design, set_dont_touch, etc. to synthesis each submodules and then synthesis the top module. For this usage we only need invoke RC license for one time; if we read one submodule, and use RC to synthesis; then read another submodule to synthesis, etc. This will invoke RC license for many times. If the license is not enough, it may be not suitable.

 So I want to know whether RC support this usage (like DC to read the whole large design for one time and then synthesis each submodules/top modules with bottom-up method) or not.

Thanks.