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RC: clock gating

Yemelya

Hello,

What is the right way to insert clock gating in RC script?


I found the following flag:
               set_attribute lp_insert_clock_gating true

Is it enough or there is something else needed?

How should I translate the following instructions from DC for RC:

 set_clock_gating_style -sequential_cell latch \
 -control_point after \
 -control_signal scan_enable \
 -minimum_bitwidth 8 \
 -observation_logic_depth 6

 compile_ultra -gate_clock


Thank you very much!!!
Boris

 

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