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RTL_compiler SDF

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Hi,

I need to simulate a gate-level netlist from RC 4.2.2
Can anybody knows how to generate an
sdf file from RC?

I've used the "write_sdf" command but the program says
that it's obsolete and doesn't accept any option.
Moreover the RC documentation doesn't tell
anything about "write_sdf"

Thank you.


Originally posted in cdnusers.org by giohdl
Parents

  • Unit delay can lead to you spending time debugging issues that don't exist. Avoid like Martha Stewart's stock tips ;-)

    Since you can't really build an SDF that will realistically reflect your final timing atleast until CTS is done, then here are two alternate solutions that I've used but no-one has suggested thus far:

    1) Create and compile a modified version of your verilog/vhdl gate library with 1nS clk->q (or qn etc) on flops (and latches), then use zero delay for combinatorial cells. Design will now function accurately pre-layout.

    2) Alternately why not create a dummy SDF that attaches delay values to specific cell types rather than specific instances? You can do this quite simply. The following example will annotate a 1ns delay to all flops in the design that are of type "floppy"...

    (DELAYFILE
    (SDFVERSION "2.1")
    (DESIGN "dodgy")
    (DATE "17-May-2006")
    (VENDOR "Shoddy Devices Inc")
    (PROGRAM "Manually created. Annotated all DFFs with CP->Q of 1:1:1")
    (VERSION "1")
    (DIVIDER /)
    (VOLTAGE 1.65:1.65:1.65)
    (PROCESS "1.5:1.5:1.5")
    (TEMPERATURE 125:125:125)
    (TIMESCALE 1 ns)
    (CELL
    (CELLTYPE "floppy" )
    (INSTANCE * )
    (DELAY
    (ABSOLUTE
    (IOPATH CP Q (1:1:1) (1:1:1))
    )
    )
    )
    )

    At "Shoddy Devices Inc", we've used both methods successfully. However the second method might be simulator depedent. I'd recommend the first method (unless your vendor doesn't give you simulator library source code).

    HTH

    Crispy Duck


    Originally posted in cdnusers.org by crispy_duck
Reply

  • Unit delay can lead to you spending time debugging issues that don't exist. Avoid like Martha Stewart's stock tips ;-)

    Since you can't really build an SDF that will realistically reflect your final timing atleast until CTS is done, then here are two alternate solutions that I've used but no-one has suggested thus far:

    1) Create and compile a modified version of your verilog/vhdl gate library with 1nS clk->q (or qn etc) on flops (and latches), then use zero delay for combinatorial cells. Design will now function accurately pre-layout.

    2) Alternately why not create a dummy SDF that attaches delay values to specific cell types rather than specific instances? You can do this quite simply. The following example will annotate a 1ns delay to all flops in the design that are of type "floppy"...

    (DELAYFILE
    (SDFVERSION "2.1")
    (DESIGN "dodgy")
    (DATE "17-May-2006")
    (VENDOR "Shoddy Devices Inc")
    (PROGRAM "Manually created. Annotated all DFFs with CP->Q of 1:1:1")
    (VERSION "1")
    (DIVIDER /)
    (VOLTAGE 1.65:1.65:1.65)
    (PROCESS "1.5:1.5:1.5")
    (TEMPERATURE 125:125:125)
    (TIMESCALE 1 ns)
    (CELL
    (CELLTYPE "floppy" )
    (INSTANCE * )
    (DELAY
    (ABSOLUTE
    (IOPATH CP Q (1:1:1) (1:1:1))
    )
    )
    )
    )

    At "Shoddy Devices Inc", we've used both methods successfully. However the second method might be simulator depedent. I'd recommend the first method (unless your vendor doesn't give you simulator library source code).

    HTH

    Crispy Duck


    Originally posted in cdnusers.org by crispy_duck
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