Hi,I need to simulate a gate-level netlist from RC 4.2.2Can anybody knows how to generate ansdf file from RC?I've used the "write_sdf" command but the program says that it's obsolete and doesn't accept any option. Moreover the RC documentation doesn't tellanything about "write_sdf"Thank you.
Hi giohdl,The write_sdf is an unsupported command, but it should work to give you a basic SDF. The syntax is:write_sdf > filenameThere's another way to get SDF is to use BuildGates (bgx_shell) from RC package. The basic script is:invoke BuildGates: bgx_shellread_dotlib your_libraryread_verilog -st your_netlistwrite_sdf file_name
Thank you synthman,I'll try with BuildGates becauseI need to specify some optionin the SDF file.
Hi Giohdl,Another way is to simulate without sdf (i.e. 0 delay, unit delay etc). Usually, this is enough. What is the use of timing before P&R?Regards,Eng Han
Hi EngHan,I think you're right in general. My circuit contains several interconnected FSMs so I've preferred to simulate before P&R avoiding zero delays in cells. Regards,Giohdl
Unit delay can lead to you spending time debugging issues that don't exist. Avoid like Martha Stewart's stock tips ;-)Since you can't really build an SDF that will realistically reflect your final timing atleast until CTS is done, then here are two alternate solutions that I've used but no-one has suggested thus far:1) Create and compile a modified version of your verilog/vhdl gate library with 1nS clk->q (or qn etc) on flops (and latches), then use zero delay for combinatorial cells. Design will now function accurately pre-layout.2) Alternately why not create a dummy SDF that attaches delay values to specific cell types rather than specific instances? You can do this quite simply. The following example will annotate a 1ns delay to all flops in the design that are of type "floppy"...(DELAYFILE (SDFVERSION "2.1") (DESIGN "dodgy") (DATE "17-May-2006") (VENDOR "Shoddy Devices Inc") (PROGRAM "Manually created. Annotated all DFFs with CP->Q of 1:1:1") (VERSION "1") (DIVIDER /) (VOLTAGE 1.65:1.65:1.65) (PROCESS "1.5:1.5:1.5") (TEMPERATURE 125:125:125) (TIMESCALE 1 ns) (CELL (CELLTYPE "floppy" ) (INSTANCE * ) (DELAY (ABSOLUTE (IOPATH CP Q (1:1:1) (1:1:1)) ) ) ))At "Shoddy Devices Inc", we've used both methods successfully. However the second method might be simulator depedent. I'd recommend the first method (unless your vendor doesn't give you simulator library source code).HTHCrispy Duck