How to force RTL compiler to use a particular net name

 Hi,

I have a RTL which after synthesis looks as in  the snippet  mentioned below..

 ===================================

wire [2:0] seed_inp;
 wire [2:0] seed_outp;

output[2:0] seed_outp;

  wire scan_5_q, scan_9_q, scan_10_n_0, scan_10_q, scan_11_n_0,
       scan_11_q, scan_12_n_0, scan_12_q;
  wire scan_fix0_6_n_0, scan_fix0_6_n_1, scan_fix0_6_q,
       scan_fix0_8_n_6, scan_fix0_8_n_8, scan_fix0_8_n_14,
       scan_fix1_2_n_0, scan_fix1_2_q;
  df1qpdw scan_10_q_reg(.CP (clk), .D (scan_10_n_0), .Q (scan_10_q));
  mx21x2pdw scan_10_g22(.D0 (seed_inp[2]), .D1 (scan_10_q), .S0
       (scan), .Z (scan_10_n_0)); 

....

.....

==================================================

I wanted RTL compiler to take the above sinppet as

df1qpd scan_8_q_reg(.CP (clk), .D (seed_outp[2]), .Q (scan_8_q)); 

mx21x2pd scan_8_g20(.D0 (seed_inp[2]), .D1 (scan_8_q), .S0
       (scan), .Z (seed_outp[2]));

==================================================

Functionality wise both are same but I am getting unnconnected  in the netlist because of this issue..

 wire [2:0] seed_inp;
 wire [2:0] seed_outp;

Is as written in the RTL and scan_9* scan_10* etc are as written out by RTL compiler after synthesis.

Is there a way I can force the RTL compiler not to use its own wire names but to retain the wire names as written in RTL ?

Regards,

-DN