constraining between ports and clock domain

Clock object is a valid object of the -to option. Look at the 'exceptions' attribute of the cost group to see if any path group exist. If the path_group does exist, look at the 'paths' attribute of the path_group to see if there is any path.

The cost group is not a constraint it is a grouping mechanism to direct the optimization and facilitate reporting.

Here are a few things you may want to make check

- Do you have an input delay define on your input port?
- If you run report timing -from do you get a path to the clk_design clock reported?
- Do you have any false path from input to that clock (sometime used when only working on FF to FF paths)
- Do you have any path_group command which might move those path to a different group?
for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group.

Thanks,
Eric.

I see following:

- cost_group input_to_clk_design exists

[b]rc:/> ls -attribute /designs/*/cost_groups/input_to_clk_design[/b]
/designs//timing/cost_groups/input_to_clk_design (cost_group)
Attributes:
exceptions = /designs//timing/exceptions/path_groups/input_to_clk_design_path

[b]rc:/> ls -attribute /designs/*/exceptions/path_groups/input_to_clk_design_path[/b]
/designs//timing/exceptions/path_groups/input_to_clk_design_path (exception)
Attributes:
cost_group = /designs//timing/cost_groups/input_to_clk_design
domain =
exception_type = path_group
from_points = /designs//ports_in/...
paths = specify_paths -from {/designs//ports_in* ...
priority = 90
to_points = /designs//timing/clock_domains/domain_1/clk_design
rc:/>

Now report timing -cost_group input_2_clk_design


Shall I define the clock with "domain"?

The last sentence in the previous posting is incomplete:

[b]report timing -cost_group input_to_clk_design[/b]

gives me

no paths found.

if you pick one of the input port and do report timing -from input_port_name, what do you get?

report timing -from /designs//ports_in/

Exception : 'path_disables/_line_2563'
Timing slack : UNCONSTRAINED
Start-point :
End-point :

(u) : Net has unmapped pin(s).

It seems it is still unconstrained.

I have used following commands:
1. create_clock -period $period -waveform [ list $rise $fall ] [ get_ports {clk_design} ] -domain clk_design
2. define_cost_group -name input_to_clk_design
3. path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path

report timing -cost_group input_to_clk_design

tells me no path found.

What version of RC do you use? Do you have any path from input ports that goes to registers clocked by clock clk_design? Try this command to see where the input port fanouts to:

fanout -end

yes definitely I have. I have implemented this design :)

fanout -end

gives me a long list!

What am I missing here??? It must be simple..
1. create_clock
2. define_cost_group
3. path_group

What else? What am I doing wrong?

RC is 6.1.

You need to define input delay with external_delay command. If you don't have that, report timing will show the path as unconstrained, but it would show the path from input to register.

Try to report timing from register to register, if it shows no path, then it might be something wrong with the library.

external_delay helped.

I did not do it. Instead, I applied "dc::set_input_delay" to an external pin.
It is not enough, it seems so. What you think?