constraining between ports and clock domain

dc::set_input_delay should work, how do you apply it?

set_input_delay $delay -clock clk_designl $inputs

it is called from an SDC file. I have written in the previous posting to imply that I have used an SDC style, not RC style.

Am I missing anything here?

In your previous email you wrote

1. create_clock
2. define_cost_group
3. path_group

You need to read the sdc between 1 and 2. not before 1 or after 3.

Eric.

1. create_clock is in an SDC file, called by another TCL script, using "read_sdc".
2. and 3. are in the TCL script, after the read_sdc call.

after external_delay, I have applied dc::set_input_delay again, RC tells me that external_delay is removed.
Are both commands equivalent, ie. "dc::set_input_delay" and "external_delay"?

external_delay is equivalent to both dc::set_input_delay and dc::set_output_delay. Your command sequence looks correct, not sure what the problem is without seeing all the data. If you have access to Cadence Support, send in the data.

Hi Eric, I have read all the postings and have read your last sentence in one of your previous postings again: "...for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group." That means RC covers this path. I am not at my desk now, but will check it as soon as possible. Then that means when I define cost_group for a clock domain, then I do not need to define -from "external_port" to a clock domain. I am using this tool for my first time, but it is pretty similar to Xilinx constraint mechanism. However RC is more "intelligent" about assigning clock domains. I will return you when I get news things.

Hi,
You can try the following:

include load_etc.tcl
define_cost_group -name I2C -design $DESIGN
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
foreach cg [find / -cost_group *] {
report timing -cost_group $cg >> $RPT_NAME
}

It creates path group from all inputs to registers, sampling the data from the inputs.
The clock and input delays should be defined before.

I think

path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C

is an overkill in a multi-milliongate design, because RTL Compiler by default definition will try to analye "all flipflops" in the design, which costs a lot of runtime.

IMHO, the clock domains must be grouped separately.

Hi,

I have found the reason, why I don't see that any path found for the port I have selected.

It has to do with that I have unknowingly set a "default" input delay just before the corresponding set_input_delay, which takes the port to another clock domain.

Therefore the second dc::set_input_delay does not take the port to another clock domain, unless the previous is removed. Therefore RTL Compiler does not find a path between the port and the clock domain I wanted, unless there is no "dc::set_input_delay" defined for the clock domain.

Thanks folks. your messages helped me a lot. Especially Eric's email.