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  3. constraining between ports and clock domain

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constraining between ports and clock domain

archive
archive over 18 years ago

I have a clock named "clk_design". How can I constrain all paths between input ports and this clock?

I have applied following:

define_cost_group input_to_clk_design
path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path

But when I apply report timing -cost_group input_to_clk_design, report tells me that no path group has been found.

Any ideas? What shall i give as -to option for path_group?



Originally posted in cdnusers.org by sporadic crash
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  • archive
    archive over 18 years ago

    Hi Eric, I have read all the postings and have read your last sentence in one of your previous postings again: "...for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group." That means RC covers this path. I am not at my desk now, but will check it as soon as possible. Then that means when I define cost_group for a clock domain, then I do not need to define -from "external_port" to a clock domain. I am using this tool for my first time, but it is pretty similar to Xilinx constraint mechanism. However RC is more "intelligent" about assigning clock domains. I will return you when I get news things.


    Originally posted in cdnusers.org by sporadic crash
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  • archive
    archive over 18 years ago

    Hi Eric, I have read all the postings and have read your last sentence in one of your previous postings again: "...for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group." That means RC covers this path. I am not at my desk now, but will check it as soon as possible. Then that means when I define cost_group for a clock domain, then I do not need to define -from "external_port" to a clock domain. I am using this tool for my first time, but it is pretty similar to Xilinx constraint mechanism. However RC is more "intelligent" about assigning clock domains. I will return you when I get news things.


    Originally posted in cdnusers.org by sporadic crash
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