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constraining between ports and clock domain

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I have a clock named "clk_design". How can I constrain all paths between input ports and this clock?

I have applied following:

define_cost_group input_to_clk_design
path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path

But when I apply report timing -cost_group input_to_clk_design, report tells me that no path group has been found.

Any ideas? What shall i give as -to option for path_group?



Originally posted in cdnusers.org by sporadic crash
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  • Hi,

    I have found the reason, why I don't see that any path found for the port I have selected.

    It has to do with that I have unknowingly set a "default" input delay just before the corresponding set_input_delay, which takes the port to another clock domain.

    Therefore the second dc::set_input_delay does not take the port to another clock domain, unless the previous is removed. Therefore RTL Compiler does not find a path between the port and the clock domain I wanted, unless there is no "dc::set_input_delay" defined for the clock domain.

    Thanks folks. your messages helped me a lot. Especially Eric's email.


    Originally posted in cdnusers.org by sporadic crash
Reply

  • Hi,

    I have found the reason, why I don't see that any path found for the port I have selected.

    It has to do with that I have unknowingly set a "default" input delay just before the corresponding set_input_delay, which takes the port to another clock domain.

    Therefore the second dc::set_input_delay does not take the port to another clock domain, unless the previous is removed. Therefore RTL Compiler does not find a path between the port and the clock domain I wanted, unless there is no "dc::set_input_delay" defined for the clock domain.

    Thanks folks. your messages helped me a lot. Especially Eric's email.


    Originally posted in cdnusers.org by sporadic crash
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