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Reading HDL files in RC

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Hi.
I'm having problems migrating from DC to RC in terms of reading HDL files.

1. I have a directory with subdirectories which include .v files - when I specify the main directory as the HDL search path, RC doesn't read the .v files under the subdirectories - any idea why?
The manual says it works like the search in unix therefore I don't understand why it doesn't try to read the subdirectories.
2. I have .v files which have commands like `include ../../ - when running RC, RC moves to a directory of its own with no regard to where the command was run from (unlike DC where if I run it from a certain directory, this directory is the reference for finding other files in case I use realtive statements such as ..) - therefore, those realtive `include commands doesn't work - any idea how to solve the problem?

Thank you in advance,
Adi.


Originally posted in cdnusers.org by adi_j

  • adi_j,
    As you have surmised, RC will not look at subdirectories recursively to find the HDL files, you will have to specify each subdirectory in the hdl_search_path attribute in order to get RC to look for source code in those directories. As for your second question, make sure that when you set the hdl_search_path attribute, you include "." in the path, otherwise the relative paths will on search for HDL starting at the places you specify in hdl_search_path. So in order to get these to work, do the following:

    set_attr hdl_search_path {. /home/my_proj/hdl_dir_name}

    Hope this helps.


    Originally posted in cdnusers.org by jflieder

  • Hello guy, i have struct with a problem in my project. I request someone to help me

    I have read more than two hdl files after synthesize an error occured during report power saying multiple design to read.

    I am using cadence digital.

    thanks in advance

  • Hi nagarjunsingir,

    clearly, you have elaborated more than one design; possibly be accident or by design. Either way, 'report power' needs to know what design you want to report power for. Such option is clearly outlined when you do

     report power -help

     or in the command reference manual

    hope this helps,

    gh-

  •  Thank you very much sir for your reply. Actually i am doing my project on reversible logic for designing flipflops. so firstly i have made all required gates library then i have used these gates to build flipflops using verilog in cadence digital. If i use more than two or three gates to build flipflops, then during synthesis an error message is displayed saying that too many designs to give power report.

     

     

     

    once again thanks for ur reply sir

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