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sub architecture selection

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In a block with deep asynchronous logic, there are some multiplier stages. I synthesized this block stand-alone and "report datapath" does not show me a multiplier architecture for it. Then I have applied following pragma:

assign some_prod[24:0] = {15'h0,some_term1[9:0]} * /* cadence sub_arch booth */ {{10{some_term2[14]}},some_term2[14:0]};

Please note the sign extension for the 2nd term.

Neither elab nor "synthesize -to_generic -effort high" shows me an information about this setting. The results with pragma above are without pragma are the same, ie. pragma does not seem to have an effect.

set_attr user_sub_arch booth [find / -design my_design]

does not work, because the attribute can be assigned only to subdesigns.

The reason why I do this experiment in a stand-alone synthesis is that the runtime of the complete system takes ca. 6 hours.

RC is v06.20-p003_1.

Can the HDL coding style affect the mechanism of inferring synthetic operators?


Originally posted in cdnusers.org by sporadic crash
Parents

  • Hi Sporadic Crash,

    I have never used this pragma and, to be honest, I am not much of a fan of them but this one definitely peeked my curiosity. I made some minor mods to the code you posted since there were a couple typos. Hopefully this is not the cause of my success. I ran RC v07.10-s009_1 and the following simple script

    set_attr library tutorial.lbr
    read_hdl -v2001 booth.v
    elab
    report datapath
    synth -to_mapped
    report datapath

    both report datapath displayed booth. I tried it without the pragma and it showed non-booth. Pretty cool !!!
    Though I have been brain washed :) and converted to the very_slow to very_fast approach RC uses. Makes my life easier . . .

    Here is the HDL I used which should be almost identical to the one you posted

    module mult_kernel #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output [WIDTH_A*WIDTH_B-1:0] prod
    );

    assign prod = terma * /* cadence sub_arch booth */ termb;

    endmodule

    module mult_prm #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input clk_data,
    input rst_data_n,
    input enable,
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output reg [WIDTH_A*WIDTH_B-1:0]prod
    );

    reg [WIDTH_A-1:0] terma_int;
    reg [WIDTH_B-1:0] termb_int;
    wire [WIDTH_A*WIDTH_B-1:0] prod_int;

    always @(posedge clk_data)
    if (rst_data_n)
    begin
    terma_int <= 0;
    termb_int <= 0;
    end
    else if (enable)
    begin
    terma_int <= terma;
    termb_int <= termb;
    end // if (enable)

    mult_kernel #(WIDTH_A, WIDTH_B) my_mult (terma_int, termb_int, prod_int);

    always @(posedge clk_data)
    if (!rst_data_n)
    prod <= 0;
    else if (enable)
    prod <= prod_int;

    endmodule

    happy thanksgiving,
    gh-


    Originally posted in cdnusers.org by grasshopper
Reply

  • Hi Sporadic Crash,

    I have never used this pragma and, to be honest, I am not much of a fan of them but this one definitely peeked my curiosity. I made some minor mods to the code you posted since there were a couple typos. Hopefully this is not the cause of my success. I ran RC v07.10-s009_1 and the following simple script

    set_attr library tutorial.lbr
    read_hdl -v2001 booth.v
    elab
    report datapath
    synth -to_mapped
    report datapath

    both report datapath displayed booth. I tried it without the pragma and it showed non-booth. Pretty cool !!!
    Though I have been brain washed :) and converted to the very_slow to very_fast approach RC uses. Makes my life easier . . .

    Here is the HDL I used which should be almost identical to the one you posted

    module mult_kernel #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output [WIDTH_A*WIDTH_B-1:0] prod
    );

    assign prod = terma * /* cadence sub_arch booth */ termb;

    endmodule

    module mult_prm #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input clk_data,
    input rst_data_n,
    input enable,
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output reg [WIDTH_A*WIDTH_B-1:0]prod
    );

    reg [WIDTH_A-1:0] terma_int;
    reg [WIDTH_B-1:0] termb_int;
    wire [WIDTH_A*WIDTH_B-1:0] prod_int;

    always @(posedge clk_data)
    if (rst_data_n)
    begin
    terma_int <= 0;
    termb_int <= 0;
    end
    else if (enable)
    begin
    terma_int <= terma;
    termb_int <= termb;
    end // if (enable)

    mult_kernel #(WIDTH_A, WIDTH_B) my_mult (terma_int, termb_int, prod_int);

    always @(posedge clk_data)
    if (!rst_data_n)
    prod <= 0;
    else if (enable)
    prod <= prod_int;

    endmodule

    happy thanksgiving,
    gh-


    Originally posted in cdnusers.org by grasshopper
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