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sub architecture selection

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In a block with deep asynchronous logic, there are some multiplier stages. I synthesized this block stand-alone and "report datapath" does not show me a multiplier architecture for it. Then I have applied following pragma:

assign some_prod[24:0] = {15'h0,some_term1[9:0]} * /* cadence sub_arch booth */ {{10{some_term2[14]}},some_term2[14:0]};

Please note the sign extension for the 2nd term.

Neither elab nor "synthesize -to_generic -effort high" shows me an information about this setting. The results with pragma above are without pragma are the same, ie. pragma does not seem to have an effect.

set_attr user_sub_arch booth [find / -design my_design]

does not work, because the attribute can be assigned only to subdesigns.

The reason why I do this experiment in a stand-alone synthesis is that the runtime of the complete system takes ca. 6 hours.

RC is v06.20-p003_1.

Can the HDL coding style affect the mechanism of inferring synthetic operators?


Originally posted in cdnusers.org by sporadic crash
Parents

  • Hi Grasshopper,

    the distributed approach has an incremental tech mapping as you see. I cannot tell the reason for company reasons.
    I have removed the 4th part (generic synthesis) which leads that step 5 performs full synthesis. No, there is no change in the architecture.

    I think this selection happens during elaboration time. As you see, elab report tells me the architecture will be very_fast but report datapath tells me it is not. OTOH, RTL Compiler docs tell me that Booth arch is selected automatically only if WIDTH > 13. I don't have it here.

    Grasshopper, do you have specail Cadence env var or special attrib for that?


    Originally posted in cdnusers.org by sporadic crash
Reply

  • Hi Grasshopper,

    the distributed approach has an incremental tech mapping as you see. I cannot tell the reason for company reasons.
    I have removed the 4th part (generic synthesis) which leads that step 5 performs full synthesis. No, there is no change in the architecture.

    I think this selection happens during elaboration time. As you see, elab report tells me the architecture will be very_fast but report datapath tells me it is not. OTOH, RTL Compiler docs tell me that Booth arch is selected automatically only if WIDTH > 13. I don't have it here.

    Grasshopper, do you have specail Cadence env var or special attrib for that?


    Originally posted in cdnusers.org by sporadic crash
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