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  3. CCD check fails as Encounter cannot parse a design file...

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CCD check fails as Encounter cannot parse a design file which has a "generate" block in it

dp2402
dp2402 over 13 years ago

Hello all,

I am currently running a CONFORMAL (R) Constraint Designer v10.10 check for an IP which consists several *.v files.

In one of the .v files the "generate" statement has been used -- This is causing an error while I run my CCD script.

-----------------
Error msg given by compiler:

// Parsing file ~hdl/abc.v ...
// Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard
// In line 235, file '~hdl/abc.v'
// Error: Fail to read design.
// Read design summary: Error: 1, Warning: 0, Note: 0
-----------------

CCD script which reads the design file:

read design -verilog2k -define <company_tech_name>\
-root <....> \
-parameter <...> \
hdl/some_file.v \
hdl/abc.v \
hdl/some_file.v \
-lastmod -noelab

-------------------------

Please throw some light on the RTL13.6 error message and tell me which switch I shall use witn the "read design" command so that the error message regarding use of "generate" statement in design dosen't show up?

Hope I am clear in the explanation!

Thanks

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  • Shalom B
    Shalom B over 13 years ago

    A standalone generate block is one in which the generate construct contains content outside a generate-if/case/for.

     Example:

    generate

    wire x;

    endgenerate

    The 'wire x;' declaration does not appear inside a generate if/for/case.

    This is legal in Verilog-2001, but not in Verilog-2005 and SystemVerilog.

    Maybe Conformal has a switch to tell it to use the 2001 version instead of the 2005 versio.

    Or you can tell Conformal to treat this as a warning instead of an error.

    Shalom

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  • Shalom B
    Shalom B over 13 years ago

    A standalone generate block is one in which the generate construct contains content outside a generate-if/case/for.

     Example:

    generate

    wire x;

    endgenerate

    The 'wire x;' declaration does not appear inside a generate if/for/case.

    This is legal in Verilog-2001, but not in Verilog-2005 and SystemVerilog.

    Maybe Conformal has a switch to tell it to use the 2001 version instead of the 2005 versio.

    Or you can tell Conformal to treat this as a warning instead of an error.

    Shalom

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