Hello all,I am currently running a CONFORMAL (R) Constraint Designer v10.10 check for an IP which consists several *.v files.In one of the .v files the "generate" statement has been used -- This is causing an error while I run my CCD script.-----------------Error msg given by compiler:// Parsing file ~hdl/abc.v ...// Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard// In line 235, file '~hdl/abc.v'// Error: Fail to read design.// Read design summary: Error: 1, Warning: 0, Note: 0-----------------CCD script which reads the design file:read design -verilog2k -define <company_tech_name>\-root <....> \-parameter <...> \hdl/some_file.v \hdl/abc.v \hdl/some_file.v \-lastmod -noelab-------------------------Please throw some light on the RTL13.6 error message and tell me which switch I shall use witn the "read design" command so that the error message regarding use of "generate" statement in design dosen't show up?
Hope I am clear in the explanation!
Just when I thought my problem is solved, CCD now says that RTL13.6 is an unknown rule!
But if I run the script without the 'set rule handling ....', compiler gives error:
// Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard
:( Can't understand what's happening!