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synthesis System Verilog design

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Hi there,

I am a new user in System Verilog and wish to gain some help here.
Do anyone know how to synthesis System Verilog design? Which CAD tool should I use?and how?


Originally posted in cdnusers.org by SHL
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  • Hi SHL,

    sounds like you never read the RTL to me. In my case it was quite simple:

    > read_hdl -sv {file1.v file2.v file3.v }

    If you cannot find the file, it has little to do with SV. Check your hdl_search_path and the paths you entered.

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper
Reply

  • Hi SHL,

    sounds like you never read the RTL to me. In my case it was quite simple:

    > read_hdl -sv {file1.v file2.v file3.v }

    If you cannot find the file, it has little to do with SV. Check your hdl_search_path and the paths you entered.

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper
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