synthesis System Verilog design

Hi SHL.

RTL Compiler has pretty extensive support of the System Verilog(IEEE 1800) syntheiszable subset. The use is pretty simple as far as I am concerned; simply add the -sv switch when you do read_hdl and that is all I had to do.

gh-

hi gh,

Actually i have tried to use Altera Quartus and Synplify Pro to synthesis my SV design. I added the .sv file when read_hdl, but when i start to run, it complain that no HDL files found.
so i was wondering whether the process of synthesis VHDL file is the same as SV file or not.
Do you have any proper user guide to synthesis a SV file? mind to sent me?
thank you

Hi SHL,

sounds like you never read the RTL to me. In my case it was quite simple:

> read_hdl -sv {file1.v file2.v file3.v }

If you cannot find the file, it has little to do with SV. Check your hdl_search_path and the paths you entered.

good luck,
gh-

Hi gh,

I am a little bit confused here. I thought that a system verilog code will have .sv extension after its name? but you just mention
{file1.v file2.v file3.v }.... ?

SHL,

a file can take any extension you want. Different design teams use different design practices and naming conventions. Some use .v, .v2k., .sv, .vg, .VG, .VRL, .VHD, .vhd, .verilog, .VLOG, .rtl, etc. You catch the drift... The tool does not care about the extension you choose but you do need to tell the tool what HDL language you are using hence the '-sv' switch needed in your read_hdl command.

hope this helps,
gh-

hi gh,
Thanks for the help. I think Synplify Pro 8 doesn't recognize .sv file. After i change my file's extention to .v and use the -sv switch, it can synthesis now.