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synthesis System Verilog design

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Hi there,

I am a new user in System Verilog and wish to gain some help here.
Do anyone know how to synthesis System Verilog design? Which CAD tool should I use?and how?


Originally posted in cdnusers.org by SHL
Parents

  • SHL,

    a file can take any extension you want. Different design teams use different design practices and naming conventions. Some use .v, .v2k., .sv, .vg, .VG, .VRL, .VHD, .vhd, .verilog, .VLOG, .rtl, etc. You catch the drift... The tool does not care about the extension you choose but you do need to tell the tool what HDL language you are using hence the '-sv' switch needed in your read_hdl command.

    hope this helps,
    gh-


    Originally posted in cdnusers.org by grasshopper
Reply

  • SHL,

    a file can take any extension you want. Different design teams use different design practices and naming conventions. Some use .v, .v2k., .sv, .vg, .VG, .VRL, .VHD, .vhd, .verilog, .VLOG, .rtl, etc. You catch the drift... The tool does not care about the extension you choose but you do need to tell the tool what HDL language you are using hence the '-sv' switch needed in your read_hdl command.

    hope this helps,
    gh-


    Originally posted in cdnusers.org by grasshopper
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