How to set_current_module in RTL Compiler??

Hi Pradeep,

Try the following:

edit_netlist new_instance -name /designs/subdesign_promoted_top /designs/topdesign

There are more options for "edit_netlist new_instance" in the manual

Regards,
Max

Sorry, tipo:
edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign

Thanks Stalker,

I will try this tomorrow, when I am in office..

But what should I do with the existing subdesign in the topdesign..?
will that be overwritten?

Or should I first remove the existing subdesign, and then create a new instance using the subdesign_promoted_top?

Can you please tell me if possible, about how merging takes place...

Thanks,
Pradeep

You can continue working with you topdesign as usual, the only thing, that you can't omit the design name in the commands, for example:
write_hdl topdesign > top.v
and not
write_hdl > top.v
I don't know exactly how the new instance is linked, but I think the subdesign_promoted_top is needed for correct work.

Hi Max,

I tried using this...
edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign

now on the topdesign I have an unconnected instance in the hierarchy,  called SUBDESIGN_INST_NAME

If I try to optimize, since this instance is unconnected, and not driving any ports, the instance is removed by synthesis.

------
I also tried the following:

The hierarchy looks like this:
/designs/topdesign/instances_hier/xxxx
/designs/topdesign/instances_hier/subdesign  ----- this is promoted to subdesign_promoted_top
/designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign


now I removed subdesign
rm /designs/topdesign/instances_hier/subdesign

So the hierarchy now looks like this:
/designs/topdesign/instances_hier/xxxx
/designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign

then I have run 'synthesize'... But however the tool sees /designs/topdesign/instances_hier/SUBDESIGN_INST_NAME, not driving any ports and optimizes it away.... but doesnt link it to topdesign!! :(

----

I am still not sure, how to link the designs....

Hi Pradeep,

have you tried the change_link command. I have used this in the past in a similar flow with pretty good success. I think the key is that the pin names have to match.

gh-

Hi gh,

yes,  change_link works...!
i was just trying that and got ur mail too :)

thanks n regards,
pradeep

Hello, 

Me too I am trying to synthesize subdesigns because my vhdl code is too big. So, I need to put to a top-level every instance of my design and so on use the command derive_environment.

Please can you help me to use this command. Where I write :
rc :> derive_environment /designs/my_top_design/instances_hier/my_subdesign_to_put_to_top_level
the terminal is block !!

This command take a long time or there is a problem with it ? 

How big is  /designs/my_top_design/instances_hier/my_subdesign_to_put_to_top_level ?

What exactly is your goal ? Can you describe what your flow is ?

gh-

My goal is to make the low power multi vdd synthesis of my design : design/top_rs232

I have 200 000 gates to synthesize and I work on the server of my school. I can't make the synthesis directly because of this server so I want to elaborate all the design and synthesize each blocks separately. After I will read all the .v file and redo the synthesis which now the server can support.