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How to set_current_module in RTL Compiler??

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Hi all,

I need to perform synthesis of a sub-block of the design. And then merge it with the top design.
I am using RTL Compiler.

In pks or build gates this was simple, we had the command set_current_module .. and one can then perform synthesis on a subdesign.

There seems to be no direct equivalent of set_current_module in RTL Compiler.

I found one command in RTL Comiler, derive_environment.
This promotes a subdesign to a topdesign.
So in design database we will now have
/designs/topdesign
/designs/subdesign_promoted_top

The synthesis which I perform on /designs/subdesign_promoted_top is now independent of actual topdesign.

This  works. But how can I later merge the
/designs/subdesign_promoted_top
into
/designs/topdesign ??

I see no way to do this in the userguide!

Can someone help me?

Thanks in advance,
Pradeep


Originally posted in cdnusers.org by spveer
Parents

  • My goal is to make the low power multi vdd synthesis of my design : design/top_rs232

    I have 200 000 gates to synthesize and I work on the server of my school. I can't make the synthesis directly because of this server so I want to elaborate all the design and synthesize each blocks separately. After I will read all the .v file and redo the synthesis which now the server can support.   

Reply

  • My goal is to make the low power multi vdd synthesis of my design : design/top_rs232

    I have 200 000 gates to synthesize and I work on the server of my school. I can't make the synthesis directly because of this server so I want to elaborate all the design and synthesize each blocks separately. After I will read all the .v file and redo the synthesis which now the server can support.   

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