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Multi corner workaround with RC?

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Hi,

I need advice related to WC and WCL corners.  Thanks.

At very small geometry, a std cell delay can be slower with decreasing temperature.  As a result, we have a new corner named WCL. It is the same as WC except that temperature is at -40 degree and not 125 degree. Compare between WC and WCL, a std cell is not always slower or faster at one corner.  As delays are modelled as 7x7 table for rise/fall/rise_transition/fall_tranisiton, a cell can be faster/slower in some of the entries at WC or WCL.

My question is how do I get the best possible result in term of timing, leakage, dynamic power and area with RC.  The easy answer is to use multi-corner approach that is available in SoC. But multi-corner is not available in RC and I think runtime will increase.

Any workaround you can recommend ?

Regards,
Eng Han


Originally posted in cdnusers.org by EngHan
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  • Hi EngHan,

    I had a similar issue and used the power_library attribute to address this. The attribute allows you to specify a different corner library for the power analysis. This can be specially important when using multiVT libraries since some libraries show very little difference in leakage in such low temperatures.

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper
Reply

  • Hi EngHan,

    I had a similar issue and used the power_library attribute to address this. The attribute allows you to specify a different corner library for the power analysis. This can be specially important when using multiVT libraries since some libraries show very little difference in leakage in such low temperatures.

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper
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