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Multi corner workaround with RC?

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Hi,

I need advice related to WC and WCL corners.  Thanks.

At very small geometry, a std cell delay can be slower with decreasing temperature.  As a result, we have a new corner named WCL. It is the same as WC except that temperature is at -40 degree and not 125 degree. Compare between WC and WCL, a std cell is not always slower or faster at one corner.  As delays are modelled as 7x7 table for rise/fall/rise_transition/fall_tranisiton, a cell can be faster/slower in some of the entries at WC or WCL.

My question is how do I get the best possible result in term of timing, leakage, dynamic power and area with RC.  The easy answer is to use multi-corner approach that is available in SoC. But multi-corner is not available in RC and I think runtime will increase.

Any workaround you can recommend ?

Regards,
Eng Han


Originally posted in cdnusers.org by EngHan
Parents

  • Hi GH,

    I think you misunderstood my problem. It has nothing to do with DVFS. I am not using DVFS, nor multi-voltage.

    I try to simplify my problem here again with a few lines. I hope it will be clearer to everyone.

    In 65nm and below, we have a new corner : WCL. Sometime a delay/transition in WCL is worst, sometime WC is worst. So I cannot synthesis with WC nor WCL as both are not the worst case. What should I use during RC synthesis?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply

  • Hi GH,

    I think you misunderstood my problem. It has nothing to do with DVFS. I am not using DVFS, nor multi-voltage.

    I try to simplify my problem here again with a few lines. I hope it will be clearer to everyone.

    In 65nm and below, we have a new corner : WCL. Sometime a delay/transition in WCL is worst, sometime WC is worst. So I cannot synthesis with WC nor WCL as both are not the worst case. What should I use during RC synthesis?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Children
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