Stats

  • Locked Locked
  • Replies 5
  • Subscribers 61
  • Views 14064
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

RC see paths through the memories.

archive

Hi All,

I see violating paths from ports through memory (D->Q) to the register.
These paths should not appear, because memory is sequential element and all the paths to D pin should stop there, but they don't.
Have anyone saw similiar issue?
Can I just disable timing arcs from D to Q inside the memories?
Thank you in advance,


Originally posted in cdnusers.org by Stalker
Parents


  • It will depend on the lib file of the used memory.
    Memory should be described as a sequential cell for input pins be considered as end points.
    If you disable timing arcs from D to Q so true paths beginning at memory pins will be affected.

    Cristiano.


    Originally posted in cdnusers.org by clsantos
Reply


  • It will depend on the lib file of the used memory.
    Memory should be described as a sequential cell for input pins be considered as end points.
    If you disable timing arcs from D to Q so true paths beginning at memory pins will be affected.

    Cristiano.


    Originally posted in cdnusers.org by clsantos
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.