RC see paths through the memories.

It will depend on the lib file of the used memory.
Memory should be described as a sequential cell for input pins be considered as end points.
If you disable timing arcs from D to Q so true paths beginning at memory pins will be affected.

Cristiano.

I have seen that in primetime before. The root cause at the time was that some test pin was controlled incorrectly (missing case analysis or incorrect case analysis) and the memory had a bypass mode feature for DFT. Has Cristiano mentioned looking at the .lib is the best to figure out why you are seeing this.

Hi Stalker,

this is pretty common and usually due to the AWT or Asynchornous Write Through functionality of memories. Usually it is used for DFT purposes but one could use it for anything else. These timing arcs can be disabled in a variety of ways:

Using SDC:

set_disable_timing [-from ] [-to ][+]

Using RC native:

set_attr enabled false [find [ find / -libcell xyz] -libarc Q*/D*]

Obviously, you want to make sure your design guarantees that you will never operate your memories in that mode since otherwise this timing violation would be real.

good luck,
gh-

As commented by gh this may be a case of AWT. The best way is indeed to disable the offending arcs.
 Another check you can make is by opening your libery files for the memory and grep for "mode" statement, you are then likely so see a functional mode and  AWT mode, for now RC does not recognize the mode statement. The presence of mode statements further will confirm that you can not solve this problem by setting consatants on test mode pins but only by disabling arcs.
-Madhu

Thanks to all,
I noticed, that case_analysis throuth AWT was missing in the latest release, I will add it back.