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RC see paths through the memories.

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Hi All,

I see violating paths from ports through memory (D->Q) to the register.
These paths should not appear, because memory is sequential element and all the paths to D pin should stop there, but they don't.
Have anyone saw similiar issue?
Can I just disable timing arcs from D to Q inside the memories?
Thank you in advance,


Originally posted in cdnusers.org by Stalker
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  • As commented by gh this may be a case of AWT. The best way is indeed to disable the offending arcs.
     Another check you can make is by opening your libery files for the memory and grep for "mode" statement, you are then likely so see a functional mode and  AWT mode, for now RC does not recognize the mode statement. The presence of mode statements further will confirm that you can not solve this problem by setting consatants on test mode pins but only by disabling arcs.
    -Madhu


    Originally posted in cdnusers.org by madhun
Reply

  • As commented by gh this may be a case of AWT. The best way is indeed to disable the offending arcs.
     Another check you can make is by opening your libery files for the memory and grep for "mode" statement, you are then likely so see a functional mode and  AWT mode, for now RC does not recognize the mode statement. The presence of mode statements further will confirm that you can not solve this problem by setting consatants on test mode pins but only by disabling arcs.
    -Madhu


    Originally posted in cdnusers.org by madhun
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