dft settings during DFT scan insertion

 Hi Tanya,

 I believe the DFT user guide is the best place to look into this. DFT has numerous nuances and providing you a one size fits all type of answer may do you more harm than good. I encourage you to discuss this with your local AEs and/or review the documentation to better tailor the answer to your needs

 hope this helps,

gh-

 hi gh,

 let me frame the question in a different way:

do we need testability logic to be inserted if we are only going for scan insertion. i am trying to do muxed scan style insertion and after that i checked the DFT rules, where around 43% registers were passing and after that i did connect scan chains in order to connect it, but i could not connect the scan chains as it said no chians available.

can you help me on this.

thanks

tanya

 Hi Tanyacool,

 I am not sure I fully understand your requirements but let me take a stab.

By default,  RC maps seqs to scan equivalent provided they pass DFT rules (TDRCs)

If you do not have control over RTL or do not want to address TDRCs in RTL you can

 (1) proceed with whatever % of TDRC-ready seqs you get

(2) use the following attribute set to force_all resulting in all seqs with scan equivalent replaced

attribute name: dft_scan_map_mode
          category: dft (controls design for test)
       object type: design
       access type: read-write
         data type: DftScanMapModeEnum
     default value: tdrc_pass
              help: DFT scan conversion mode {tdrc_pass | preserve | force_all}.
 

(3) use the command fix_dft_violations to address TDRCs 

 Note that TDRC status is tagged upon runing the command check_dft_rules

Scan replacement happens during incremental synthesis

scan connection will not happen unless your seqs have been scan replaced

gh-