Does test compaction reduces tester time or memory or both?

 Please clarify if you are referring to hardware compression (hardware inserted into the chip to split long fullscan chains into shorter scan channels), or software compaction (ATPG technique to reduce pattern count).

 I guess the answer isn't that important, because both techniques will reduce both tester time and memory, although software compaction is not nearly effective as hardware compression logic.   Software compaction nearly "free", however, as it only consumes runtime.   The only other downside to software compaction is a possible increase in the power consumption of a pattern.

 Please clarify if you are referring to hardware compression (hardware inserted into the chip to split long fullscan chains into shorter scan channels), or software compaction (ATPG technique to reduce pattern count).

 I guess the answer isn't that important, because both techniques will reduce both tester time and memory, although software compaction is not nearly effective as hardware compression logic.   Software compaction nearly "free", however, as it only consumes runtime.   The only other downside to software compaction is a possible increase in the power consumption of a pattern.