i had the doubt regarding the fact that how we can prevent the use of clock pin as a reset pin or a data pin.
do we need to do some changes in the SDC file or some attribute settings in the main rc script.
Synthesis tools cannot and should not ignore the designers intent so if the designer indicated through their HDL to use a clock as a reset, then the tools cannot ignore that without ignoring the designers intent. If the tools were to do that you would get an adder implemented when the HDL indicates a filter. Yes, that is an exterme case but it seeks to illustrate the 'why' the tool cannot ignore what the designer instructed the tool to do.
Tools can certainly warn the user about things that have potential for issues but violating the intent would render the HDL unreliable and make the tools 'psychic' ;)
hope this helps,