i had the doubt regarding the fact that how we can prevent the use of clock pin as a reset pin or a data pin.
do we need to do some changes in the SDC file or some attribute settings in the main rc script.
I am not sure I understand the question. Ultimately, what do you expect the tools to do if your HDL says
always @(posedge clk1) begin
dataout <= clk2
. . .
similarly for the reset case. The lint report (report timing -lint -verbobse) will warn you about this but it ultimately up to the user to specify the design correctly. The HDL is correct and there is no other way to implement than to use clk2 as specified in HDL so other than warning you I am not sure what else can the tools do
hope this helps,
i got your point and i strongly agree with you. But what i need is if this is the case present already in our design then will the tool still use clock as a data pin as you have mentioned above.
what my question was is there any way by the tool to avoid the use of clock as a reset pin or a data pin or it totally depends upon the designer as to how he/she is designing.
Synthesis tools cannot and should not ignore the designers intent so if the designer indicated through their HDL to use a clock as a reset, then the tools cannot ignore that without ignoring the designers intent. If the tools were to do that you would get an adder implemented when the HDL indicates a filter. Yes, that is an exterme case but it seeks to illustrate the 'why' the tool cannot ignore what the designer instructed the tool to do.
Tools can certainly warn the user about things that have potential for issues but violating the intent would render the HDL unreliable and make the tools 'psychic' ;)