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Problem with un-mapped elements

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Hi,
I am trying to run Conformal on RTL vs gate-level netlist. I have noticed that synthesis removed a FF in netlist due to that fact that its D input has been tied to 0. Howver while flattening the netlist the FF is not removed and is reported as unmapped element. As a result some comapre points fail due to the fact that this FF is in the logic cone.
By looking at schematic of golden netlist and tracing back the D input of the FF it looks like this pin is connected to other elementes named DC which shows as connection due to constraint. How can I identify which is the offendign constraitn that originated the problem. report_pin_constraint and report_dynamic_constraint command do no report any constraint.

Thanks
Maurizio Spadari  
Principal Design Engineer
NemeriX SA


Originally posted in cdnusers.org by maurizios

  • Hi Maurizio

    Are you using the following flow?

    set flatten model -seq_constant
    set flatten model -seq_constant_x_to 0
    set flatten model -gated_clock

    set system mode lec

    remodel -seq_constant -seq_constant_feedback -repeat
    map key points

    That should take care of removing the constant flop.

    A couple more notes:

    1) the runtime of the 'remodel' command was dramatically improved in 7.1 compared to 6.2 or earlier versions

    2) I have run into a couple cases lately where DC leaves a constant flop in the netlist but optimizes the fanout from that flop based on the constant value (that makes no sense to me but it's functionally correct). The solution is to use "set flatten model -nobalanced_modeling" or to add -nomap to 'set system mode lec' if the number of flops in the design is reasonable (under 50K or so).

    Chrystian


    Originally posted in cdnusers.org by croy

  • Hi Chrystian,
    thanks your suggestion worked. Unfortunately now I hit with another problem related to clock gating. I will list it in a separate post.
    Maurizio


    Originally posted in cdnusers.org by maurizios

  • Becareful using sequential propagation. Unless it has been fixed it doesn't always behave as youwould expect. The end result is too much propagation that could mask real bolean non-equilancies. Becareful if you have tied clocks and constant signals like you might have in your test logic.

    Given the issues my philosophy has been to not allow sequential optimization in synthesis and thus I won't need in when doing boolean equivalency checking.


    Originally posted in cdnusers.org by bryan

  • I am having a similar problem. In the RTL I have an 8 bit counter, but the logic never counts up beyond 16, so bits 5, 6, and 7 are removed during synthesis. For some reason, conformal will not remove bits 5, 6, and 7 when it reads in the RTL.

    I've tried 'set flatten model -all_seq_merge', but still when I run 'unmapped points -notmapped' it still reports these as unmapped. I've used '-nokeep_unreach' when reading the design, but it still keeps bits 6, and 7 around. How do I get conformal to do the same optimization that the synthesis tool performed?

    I've tried what is suggested above, but I get a ton of mismatches (don't know why yet). Is there something I can do?

  •  Hi Malexgreen,

    is it possible for you to share the RTL that has the counter. I may be able to share a similar experience but not sure from your description.

     gh-

  • Is there a way to do this securely?

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