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Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

Rafeeq2129

I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.

--> Conformal doesn't map the RTL(async neg reset) with its counterpart  in netlist(DC). 

---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch 

 **************my dofile is as follows (till it goes into lec mode)

     reset

    set log file <  >

     "sourcing project specific variables"

    set undefined cell black_box

      add notranslate filepathnames <  >

      add search path

      read library -verilog2k  

       read design -noelaborate -verilog2k -nosensitive  -golden <>

         read design -noelab -systemverilog -nosensitive -golden <>

      elaborate design -golden <>

      read design  -verilog 2k -revised <>

        set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose

 set system mode lec

 

*******************************************************************

 

please provide me the basic flow for CONFORMAL--DC netlist

 

regards,

rafeeq

 

Parents

  • Hi, Rafeeq.

    Your best bet is to start with a standard dofile script for RTL to gate compares. Hier compare is recommended but flat can also be used.

    These sample dofiles are in the "web interface" documentation. You can access them with "set web on" and then open the browser URL in PC or linux. The WI also has a good document on verifying DC netlists. Look for "LEC Verification".

    The WI has a lot of really good documents and I find them really useful.

    Here is an example dofile

    read library -verilog -replace -both <lib_files>
    read library -liberty -replace -both <lib_files>
    read design -verilog -replace -golden <design_files>
    read design -verilog -replace -revised <design_files>
    report design data
    report black box -detail
    add pin constraint 0 scan_en -golden/revised
    add ignore output scan_out -golden/revised
    set flatten model -seq_constant
    set flatten model -gated_clock
    set analyze option -auto
    set parallel option -threads 4 -norelease_license

    // Uncomment for flat compare

    // set system mode lec

    // add compared points -all

    // compare

     

    // Hier compare after this point. 

    write hier_compare dofile hier.do -replace -usage
       -constraint -noexact_pin_match -verbose
       -prepend_string "report design data; usage;
       analyze datapath -module -resourcefile <file> -verbose; usage;
       analyze datapath -verbose; usage "
       -balanced_extraction -input_output_pin_equivalence
       -function_pin_mapping
    run hier_compare hier.do -verbose

     

    -ts

Reply

  • Hi, Rafeeq.

    Your best bet is to start with a standard dofile script for RTL to gate compares. Hier compare is recommended but flat can also be used.

    These sample dofiles are in the "web interface" documentation. You can access them with "set web on" and then open the browser URL in PC or linux. The WI also has a good document on verifying DC netlists. Look for "LEC Verification".

    The WI has a lot of really good documents and I find them really useful.

    Here is an example dofile

    read library -verilog -replace -both <lib_files>
    read library -liberty -replace -both <lib_files>
    read design -verilog -replace -golden <design_files>
    read design -verilog -replace -revised <design_files>
    report design data
    report black box -detail
    add pin constraint 0 scan_en -golden/revised
    add ignore output scan_out -golden/revised
    set flatten model -seq_constant
    set flatten model -gated_clock
    set analyze option -auto
    set parallel option -threads 4 -norelease_license

    // Uncomment for flat compare

    // set system mode lec

    // add compared points -all

    // compare

     

    // Hier compare after this point. 

    write hier_compare dofile hier.do -replace -usage
       -constraint -noexact_pin_match -verbose
       -prepend_string "report design data; usage;
       analyze datapath -module -resourcefile <file> -verbose; usage;
       analyze datapath -verbose; usage "
       -balanced_extraction -input_output_pin_equivalence
       -function_pin_mapping
    run hier_compare hier.do -verbose

     

    -ts

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