I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.
--> Conformal doesn't map the RTL(async neg reset) with its counterpart in netlist(DC).
---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch
**************my dofile is as follows (till it goes into lec mode)
set log file < >
"sourcing project specific variables"
set undefined cell black_box
add notranslate filepathnames < >
add search path
read library -verilog2k
read design -noelaborate -verilog2k -nosensitive -golden <>
read design -noelab -systemverilog -nosensitive -golden <>
elaborate design -golden <>
read design -verilog 2k -revised <>
set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose
set system mode lec
please provide me the basic flow for CONFORMAL--DC netlist
Your best bet is to start with a standard dofile script for RTL to gate compares. Hier compare is recommended but flat can also be used.
These sample dofiles are in the "web interface" documentation. You can access them with "set web on" and then open the browser URL in PC or linux. The WI also has a good document on verifying DC netlists. Look for "LEC Verification".
The WI has a lot of really good documents and I find them really useful.
Here is an example dofile
read library -verilog -replace -both <lib_files>read library -liberty -replace -both <lib_files>read design -verilog -replace -golden <design_files>read design -verilog -replace -revised <design_files>report design datareport black box -detailadd pin constraint 0 scan_en -golden/revisedadd ignore output scan_out -golden/revisedset flatten model -seq_constantset flatten model -gated_clockset analyze option -autoset parallel option -threads 4 -norelease_license
// Uncomment for flat compare
// set system mode lec
// add compared points -all
// Hier compare after this point.
write hier_compare dofile hier.do -replace -usage -constraint -noexact_pin_match -verbose -prepend_string "report design data; usage; analyze datapath -module -resourcefile <file> -verbose; usage; analyze datapath -verbose; usage " -balanced_extraction -input_output_pin_equivalence -function_pin_mapping run hier_compare hier.do -verbose
Thanks for providing me the basic flow. I was able to clear the aborts / unmapped points in my design using "analyze setup" , as was suggested to me in my case request.
In the flow you mentioned, Can i use both "Flattened" and then "hierarchical flow" for my design?
How much important is resource file for the analyze datapth command ?
Glad to read.
You can use either hier or flat for compares. Hier is better for RTL to gates since it makes for small logic cone sizes and thus helps avoid aborts. Flat is suggested for gate to gate compares (if you encounter modeling or aborts gate to gate then you can try hier).
The resource file is useful for resolving aborts (and avoiding them in a CAD flow). For a one-off run with no aborts it is not needed.
thanks for information.
I was facing around 1900 aborts with the flat run, in which most of them seems to be the datapath optimizations. Hence, I fired the hier compare with the flow you suggested, along with resource file . the end result was 2 aborts.
I want to check all the equiv./non-eq/aborts of the whole design, and diagnise it. But, I'm unable to find the doc. which gives specific information on debug of hier-result. Although there is a chapter in user-guide, it mostly guides about running flow using GUI. Could you please help me on it ?
There is a lot of good debug material in the "Web Interface".
Type "SETUP> set web on" and view in a browser. See Abort Resolution and LEC Verification.
Also see the LEC debugging quickstart video: