Stats

  • Locked Locked
  • Replies 12
  • Subscribers 61
  • Views 17405
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

Rafeeq2129

I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.

--> Conformal doesn't map the RTL(async neg reset) with its counterpart  in netlist(DC). 

---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch 

 **************my dofile is as follows (till it goes into lec mode)

     reset

    set log file <  >

     "sourcing project specific variables"

    set undefined cell black_box

      add notranslate filepathnames <  >

      add search path

      read library -verilog2k  

       read design -noelaborate -verilog2k -nosensitive  -golden <>

         read design -noelab -systemverilog -nosensitive -golden <>

      elaborate design -golden <>

      read design  -verilog 2k -revised <>

        set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose

 set system mode lec

 

*******************************************************************

 

please provide me the basic flow for CONFORMAL--DC netlist

 

regards,

rafeeq

 

  •  Hi Rafeeq,

     the main problem you may have is that TCL does not have a 'prepend' command but it is hard to guess without you providing any output of what message you are getting. For a list of TCL commands, please refer to

    http://www.tcl.tk/man/tcl8.5/

    hope this helps,

    gh-

  •  You should be able to use this option with write_hier_compare_dofile in TCL. It will have to be valid TC, escaped etc.

     Maybe try with something simple first and verify it works.

    There are some small sample testcases in the installation tree:

    share/cfm/lec/demo

    If it is too much of a problem try going into VPX mode (not TCL mode):

    vpxmode

    write hier_compare dofile ...

    run hier

    tclmode

     

    -ts

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.