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RC: set_min/max_delay breaks the constrained paths

Sporadic Crash

I have used following command(s) to constraint path delays on FF->FF path:

set_max_delay -from $some_flops -to [get_pin inst/in_i*] 8

The path that goes through [get_pin inst/in_i*] ends in a target FF. However when after the SDC command above, when I try to generate a timing report, following message is coming from RTL Compiler:

 

rc:/> report timing -from [find / -inst *dat_reg*] -summary

 

 

                              Pin                                        Type      Fanout Load Slew Delay Arrival   

                                                                                          (fF) (ps)  (ps)   (ps)    

--------------------------------------------------------------------------------------------------------------------

source_inst

  dat_reg_69/CP                                                 <<<                             0             0 R 

  dat_reg_69/Q                                                       qqq          3 19.9  227  +410     410 F 

  g15476/D                                                                                             +0     410   

  g15476/Z                                                             qqq           1  7.9  327  +250     660 R 

  g15435/D                                                                                             +0     660   

  g15435/Z                                                             qqq         1  8.9  286  +398    1058 R 

  g15419/C                                                                                             +0    1058   

  g15419/Z                                                             qqq         1  8.6  174  +193    1251 F 

  g15415/E                                                                                             +0    1251   

  g15415/Z                                                             qqq          1  8.9  410  +303    1554 R 

  g15391/C                                                                                             +0    1554   

  g15391/Z                                                             qqq         3 18.3  294  +302    1856 F 

source_inst/dat_o[19]

g35169/B                                                                                               +0    1856   

g35169/Z                                                               qqq       1  8.2  276  +358    2215 F 

g34962/C                                                                                               +0    2215   

g34962/Z                                                               qqq          1  7.4  408  +257    2472 R 

g34478/B                                                                                               +0    2472   

g34478/Z                                                               qqq           4 26.8  240  +379    2851 R 

some_inst/data_i[19] 

  g4358/E                                                                                              +0    2851   

  g4358/Z                                                              qqq          1  8.9  501  +300    3150 F 

  g4348/C                                                                                              +0    3151   

  g4348/Z                                                              qqq 3 16.6  325  +337    3487 R 

  xinst/B                                                  +0    3487   

  xinst/Z                  qqq           1 43.4  342  +390    3877 R 

  inst/in_i[9] (b)                                  +0    3877 R 

--------------------------------------------------------------------------------------------------------------------

Exception    : 'path_delays/zipped_path_delay_0'    8500ps

Timing slack :    4623ps 

Start-point  : dat_reg_69/CP

End-point    : inst/in_i[9]

 

(b) : Timing paths are broken.

 

 

 

I have renamed instance and libcell names because company reasons.

Is there a way to disable the behaviour of RTL Compiler that breaks the path, when set_min/max_delay SDC command is given?
After the SDC command, the path from inst/in_i[9] until the FF will get unconstrained automatically, which I don't want.

Parents

  • Hi,

     Can you please check one thing.

    You may be applying max delay at a higher level of hierarchy. Just check that there might be sequential instance below that hierarchy.

    Try putting max delay from that lowest level of hierarchy ie: reg and to the lowest level of hierarchy that is reg.

    It may solve the problem.

     

    thanks,

    Shobhit 

Reply

  • Hi,

     Can you please check one thing.

    You may be applying max delay at a higher level of hierarchy. Just check that there might be sequential instance below that hierarchy.

    Try putting max delay from that lowest level of hierarchy ie: reg and to the lowest level of hierarchy that is reg.

    It may solve the problem.

     

    thanks,

    Shobhit 

Children
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