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Problem occurs when reading vcd in RTL Compiler

rexnyu

Dear all,

I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:

gcm.v (This is the main circuit. Module name is "gcm")

tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")

 

The command to generate vcd file is in tb.v as below:

  $dumpfile ("testb. vcd");

  $dumpvars (1, testbench.gcm_tb);

 

Here is my script for RTL compiler:

 

set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files

set_attribute library {gscl45nm.lib}

read_hdl -v2001 tb.v

elaborate

synthesize -to_mapped 

read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

write -mapped > gcm_synth.v

report power > power.txt

exit

 

 RTL compiler gives me the same power numbers with and without the VCD file. What is the reason for this? 

 

 Thank you!

 

Parents

  •  Is the VCD being read correctly?  Are a signficant number of primary inputs and flops being getting annotated?  read_vcd should give you a summary when it completes.  If it doesn't run "report power -tcf_summary". 

     I recommend reading the VCD after elaboration, not after mapping. RTL Compiler can do ungrouping, name changes, etc that can make it difficult to apply a VCD after mapping.  Your best opportinity to annotate a VCD is after elaboration.

     If you aren't getting good annotation of the sequential elements in your design, you will have to do some debug.  First, see if you can find the sequential element name in the VCD.  If it doesn't exist, figure out why it wasn't written into the VCD.  If it does exist, check the name and compare it to the name in RC.  Look for differences in the naming style.  If you aren't getting anything annotated, it could be you need to alter the read_vcd -vcd_module or -module arguments.

     Finally, be sure the lp_power_analysis_effort attribute is set to medium or high (medium is default).  If you set it to "low" the VCD data is ignored, no activity propagation is done, and defaults are used on every node.

     Good luck!

     

Reply

  •  Is the VCD being read correctly?  Are a signficant number of primary inputs and flops being getting annotated?  read_vcd should give you a summary when it completes.  If it doesn't run "report power -tcf_summary". 

     I recommend reading the VCD after elaboration, not after mapping. RTL Compiler can do ungrouping, name changes, etc that can make it difficult to apply a VCD after mapping.  Your best opportinity to annotate a VCD is after elaboration.

     If you aren't getting good annotation of the sequential elements in your design, you will have to do some debug.  First, see if you can find the sequential element name in the VCD.  If it doesn't exist, figure out why it wasn't written into the VCD.  If it does exist, check the name and compare it to the name in RC.  Look for differences in the naming style.  If you aren't getting anything annotated, it could be you need to alter the read_vcd -vcd_module or -module arguments.

     Finally, be sure the lp_power_analysis_effort attribute is set to medium or high (medium is default).  If you set it to "low" the VCD data is ignored, no activity propagation is done, and defaults are used on every node.

     Good luck!

     

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