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Problem occurs when reading vcd in RTL Compiler

rexnyu

Dear all,

I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:

gcm.v (This is the main circuit. Module name is "gcm")

tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")

 

The command to generate vcd file is in tb.v as below:

  $dumpfile ("testb. vcd");

  $dumpvars (1, testbench.gcm_tb);

 

Here is my script for RTL compiler:

 

set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files

set_attribute library {gscl45nm.lib}

read_hdl -v2001 tb.v

elaborate

synthesize -to_mapped 

read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

write -mapped > gcm_synth.v

report power > power.txt

exit

 

 RTL compiler gives me the same power numbers with and without the VCD file. What is the reason for this? 

 

 Thank you!

 

  •  Is the VCD being read correctly?  Are a signficant number of primary inputs and flops being getting annotated?  read_vcd should give you a summary when it completes.  If it doesn't run "report power -tcf_summary". 

     I recommend reading the VCD after elaboration, not after mapping. RTL Compiler can do ungrouping, name changes, etc that can make it difficult to apply a VCD after mapping.  Your best opportinity to annotate a VCD is after elaboration.

     If you aren't getting good annotation of the sequential elements in your design, you will have to do some debug.  First, see if you can find the sequential element name in the VCD.  If it doesn't exist, figure out why it wasn't written into the VCD.  If it does exist, check the name and compare it to the name in RC.  Look for differences in the naming style.  If you aren't getting anything annotated, it could be you need to alter the read_vcd -vcd_module or -module arguments.

     Finally, be sure the lp_power_analysis_effort attribute is set to medium or high (medium is default).  If you set it to "low" the VCD data is ignored, no activity propagation is done, and defaults are used on every node.

     Good luck!

     

  • Thank you for the hint! But I have a more fundamental question. Should I synthesize the testbench (tb.v) or the design file (design.v). It is giving me different number of gates... The reason why the verilog commands that are used to generate power are in the testbench is because this is the method I used in Xilinx power analyzer. Is the same method (use verilog command in the testbench) acceptable in Cadence design flow?

  • I don't think it makes sense to synthesize the testbench.  In fact, I am surprised tb.v is synthesizable at all.  tb.v does not represent hardware (I assume), so I would expect it to contain verilog constructs that cannot be synthesized.

     The VCD file can contain data for both the testbench, and the design.  You just need to tell RC, through the read_vcd options, which module you are annotating.

  • Sorry. I changed the hdl input file, here is the command I used

    read_hdl -v2001 gcm.v

     

    I also change the script according to what you suggest as below:

     

    elaborate

    read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

    synthesize -to_mapped

    write -mapped > gcm_synth.v

    report power -tcf_summary > power.txt

     

    In power.txt, I still get the same power number with and without VCD file. Here is the summary:

    ============================================================

      Generated by:           Encounter(r) RTL Compiler v07.10-p004_1

      Generated on:           Mar 28 2013  12:34:49 PM

      Module:                 gcm

      Technology library:     gscl45nm

      Operating conditions:   typical (balanced_tree)

      Wireload mode:          enclosed

    ============================================================


                         Leakage    Dynamic     Total

      Instance   Cells  Power(nW)  Power(nW)  Power(nW)

    ----------------------------------------------------

    gcm           4318 103161.839 784254.990 887416.829

      add_258_11   127   6038.327  16897.719  22936.046

      GFM            0      0.000  11282.948  11282.948

      aes_inst       0      0.000  52656.175  52656.175


    -------------------------------------------------------

    Total nets in design            : 5347 (100.00%)

    Nets asserted                   : 0 (0.00%)

    Nets computed                   : 5344 (99.94%)

    Default nets                    : 0 (0.00%)

    Clock nets                      : 0 (0.00%)

    Constant nets                   : 3 (0.06%)

    Net does not have TCF asserted  : 5347 (100.00%)

    -------------------------------------------------------

     

     The VCD file I used works fine with Xilinx power analyzer. Do I need to regenerate it using cadence ncsim?

     BTW: When I generate the VCD file, do I need to tell ModelSim the library that I am going to use in RTL Compiler?

     

  • I solved the problem. After I change the design to be synthesized from tb to gcm, I also change the way I generate the VCD file. I should use $dumpvar (0, tb.gcm_tb) instead of $dumpvar (1, tb.gcm_tb). Thank you so much!

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