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Problem occurs when reading vcd in RTL Compiler

rexnyu

Dear all,

I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:

gcm.v (This is the main circuit. Module name is "gcm")

tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")

 

The command to generate vcd file is in tb.v as below:

  $dumpfile ("testb. vcd");

  $dumpvars (1, testbench.gcm_tb);

 

Here is my script for RTL compiler:

 

set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files

set_attribute library {gscl45nm.lib}

read_hdl -v2001 tb.v

elaborate

synthesize -to_mapped 

read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

write -mapped > gcm_synth.v

report power > power.txt

exit

 

 RTL compiler gives me the same power numbers with and without the VCD file. What is the reason for this? 

 

 Thank you!

 

Parents

  • Sorry. I changed the hdl input file, here is the command I used

    read_hdl -v2001 gcm.v

     

    I also change the script according to what you suggest as below:

     

    elaborate

    read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

    synthesize -to_mapped

    write -mapped > gcm_synth.v

    report power -tcf_summary > power.txt

     

    In power.txt, I still get the same power number with and without VCD file. Here is the summary:

    ============================================================

      Generated by:           Encounter(r) RTL Compiler v07.10-p004_1

      Generated on:           Mar 28 2013  12:34:49 PM

      Module:                 gcm

      Technology library:     gscl45nm

      Operating conditions:   typical (balanced_tree)

      Wireload mode:          enclosed

    ============================================================


                         Leakage    Dynamic     Total

      Instance   Cells  Power(nW)  Power(nW)  Power(nW)

    ----------------------------------------------------

    gcm           4318 103161.839 784254.990 887416.829

      add_258_11   127   6038.327  16897.719  22936.046

      GFM            0      0.000  11282.948  11282.948

      aes_inst       0      0.000  52656.175  52656.175


    -------------------------------------------------------

    Total nets in design            : 5347 (100.00%)

    Nets asserted                   : 0 (0.00%)

    Nets computed                   : 5344 (99.94%)

    Default nets                    : 0 (0.00%)

    Clock nets                      : 0 (0.00%)

    Constant nets                   : 3 (0.06%)

    Net does not have TCF asserted  : 5347 (100.00%)

    -------------------------------------------------------

     

     The VCD file I used works fine with Xilinx power analyzer. Do I need to regenerate it using cadence ncsim?

     BTW: When I generate the VCD file, do I need to tell ModelSim the library that I am going to use in RTL Compiler?

     

Reply

  • Sorry. I changed the hdl input file, here is the command I used

    read_hdl -v2001 gcm.v

     

    I also change the script according to what you suggest as below:

     

    elaborate

    read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

    synthesize -to_mapped

    write -mapped > gcm_synth.v

    report power -tcf_summary > power.txt

     

    In power.txt, I still get the same power number with and without VCD file. Here is the summary:

    ============================================================

      Generated by:           Encounter(r) RTL Compiler v07.10-p004_1

      Generated on:           Mar 28 2013  12:34:49 PM

      Module:                 gcm

      Technology library:     gscl45nm

      Operating conditions:   typical (balanced_tree)

      Wireload mode:          enclosed

    ============================================================


                         Leakage    Dynamic     Total

      Instance   Cells  Power(nW)  Power(nW)  Power(nW)

    ----------------------------------------------------

    gcm           4318 103161.839 784254.990 887416.829

      add_258_11   127   6038.327  16897.719  22936.046

      GFM            0      0.000  11282.948  11282.948

      aes_inst       0      0.000  52656.175  52656.175


    -------------------------------------------------------

    Total nets in design            : 5347 (100.00%)

    Nets asserted                   : 0 (0.00%)

    Nets computed                   : 5344 (99.94%)

    Default nets                    : 0 (0.00%)

    Clock nets                      : 0 (0.00%)

    Constant nets                   : 3 (0.06%)

    Net does not have TCF asserted  : 5347 (100.00%)

    -------------------------------------------------------

     

     The VCD file I used works fine with Xilinx power analyzer. Do I need to regenerate it using cadence ncsim?

     BTW: When I generate the VCD file, do I need to tell ModelSim the library that I am going to use in RTL Compiler?

     

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