In RTL compiler, I have successfully used the following flow
- Read Verilog Netlist
- Read VCD Annotation Data between times t0 and t1 (Chip "Active")
- Report Power for "Active"
- Reset Design
- Read VCD Annaotation Data between times t2 and t3 (Chip "Standby")
- Report Power for "Standby"
This has worked succesfully and reported "Active" and "Standby" power is as excpected
I am now trying to improve the flow by reading the CPF file, which defines the power modes. So, now I attempting to report power for each power mode, whilst also including the VCD annotation data.
Unfortunately, this does not seem to work. As far as I can tell, the VCD annotation data is not being used in the power calculation such that the power is the same in both "Active" and "Standby".
Has anyone used this flow? Should it work?
This is somewhat strange, could you please file a case in support.cadence.com ?