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RTL Compiler: VCD Annotation and CPF

moogydmaxim

Hi,

In RTL compiler, I have successfully used the following flow

- Read Verilog Netlist

- Read VCD Annotation Data between times t0 and t1 (Chip "Active")

- Report Power for "Active"

- Reset Design

- Read VCD Annaotation Data between  times t2 and t3 (Chip "Standby")

- Report Power for "Standby"

This has worked succesfully and reported "Active" and "Standby" power is as excpected

I am now trying to improve the flow by reading the CPF file, which defines the power modes. So, now I attempting to report power for each power mode, whilst also including the VCD annotation data.

Unfortunately, this does not seem to work. As far as I can tell, the VCD annotation data is not being used in the power calculation such that the power is the same in both "Active" and "Standby".

Has anyone used this flow? Should it work?

Thanks,

 Steven

 

  •  Hi Steven,

     

    The solution to your problem would be one of the following.

     

    Solution #1: Annotate switching activities for each power mode in your cpf file. Check update_power_mode -activity_file command .

     

    Solution #2: Your flow should look something like this:

    read_cpf -library

    read_hdl 

    elaborate

    read_cpf

    read_tcf

    synth -to_generic

    //diagnostics, reports etc here

    commit cpf

    synth -to_map

     

    Notice that we read tcf (or vcd or saif) AFTER read_cpf . If you try to read it before, you won't get accurate results

     

    Hope I helped,

    Fotis

  • Hi Fotis,

    Thanks for the reply - I am trying your solution #2 - the only difference is that I am using a GL nelitst.

    Therefore, my flow is

    1) read_cpf (libraries)

    2) read_netlist

    3) read_cpf

    3) read_vcd -start_time $start -end_time $end

    4) report power # This gives expected result

    5) report pwer -mode myode # Result same as if no annotation

    6) report power # The VCD annotation data has been lost -> incorrect annotation data

    Note that when I perform command 5, it looks like a reset_design is performed and VCD data is lost. This is confirmed by repeating the report power (without mode) where I see incorrect results.

    Thanks,

    Steven.

     

  •  Hi steven,

     

    This is somewhat strange, could you please file a case in support.cadence.com ? 

     

    Regards,

    Fotis

  • Hi Fotis,

    Thanks for the feedback - it's good to have confirmation that what I am trying to work should work :-)

     When time permits, I will try with a later version of RC, and then I will pass the issue to our central EDA group, who will check further.

    Thanks again,

    Steven

     

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