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Two warnings(external_delay and CSA rejected)

20050710212

There are two kind of warnings always happened during synthesis. I checked them in the user manual but I do not know how to solve them. 

1. The following primary outputs have no clocked external delays.  As a result the timing paths leading to the ports have no timing constraints derived from clock aveforms. The'external_delay' command is used to create new external delays.
/designs/FIFO/ports_out/dataout[0]
/designs/FIFO/ports_out/dataout[10]
/designs/FIFO/ports_out/dataout[11]......


2.There is 1 CSA group in module 'FIFO_csa_cluster_33'... Rejected. Somtimes it is accepted. sometimes it is rejectd.                          What is CSA group?

Could you please give me some advieces to fix these problems?

Thank you very much.

Parents

  •  Hi 20050710212,

     (1) As the message specifies, the outputs have not clock reference hence no way to time paths ending at those outputs. You need to ask a set_output_delay statement in your SDC with a clock reference if you expect those paths to be timed

    (2) Carry Save Adder. Do a google search on it and you will get plenty of detailed information on adder architecture. Acceptance/Rejection depends on a variety of things, mainly your design constraints

    hope this helps,

    gh-

Reply

  •  Hi 20050710212,

     (1) As the message specifies, the outputs have not clock reference hence no way to time paths ending at those outputs. You need to ask a set_output_delay statement in your SDC with a clock reference if you expect those paths to be timed

    (2) Carry Save Adder. Do a google search on it and you will get plenty of detailed information on adder architecture. Acceptance/Rejection depends on a variety of things, mainly your design constraints

    hope this helps,

    gh-

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