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How to preserve the internal signal name in synthesis when using Cadence RTL compiler

Here is part of my script.

set_attribute write_vlog_preserve_net_name true

elaborate aes_fwd_top

ungroup -flatten -all

synthesize -to_mapped

write_hdl -mapped > aes_fwd_top-orig.v

But RTL compiler keeps changing my internal signal names with some random names in the verilog netlist file.

What is the proper way to use "write_vlog_preserve_net_name"? or I am using the wrong command.

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nightswhosayni over 9 years ago

Hmm....

"Topic has 0 replies and 6091 views."

Seems like there are a number of folks also having the same issue, yet "0" replies.

You would think this might have made the R&D priority list.

And here we are three years later.
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nightswhosayni over 9 years ago

Hmm....

"Topic has 0 replies and 6091 views."

Seems like there are a number of folks also having the same issue, yet "0" replies.

You would think this might have made the R&D priority list.

And here we are three years later.
Cancel
Vote Up 0 Vote Down

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